Update to rvy 0.9.10 by joncapltd · Pull Request #763 · lowRISC/mocha

joncapltd · 2026-10-22T11:42:51Z

This is an in-development update to cva6-cheri to rvy 0.9.10 support.
In addition, floating point and caches are enabled.
This has been tested on FPGA for baremetal tests (which are ported in this branch), and updated OpenSBI and UBoot and seL4 from outside of this repo. Not all assembly in this repo has been ported to 0.9.10 yet, and that which has been ported has not been tested beyond booting on FPGA.

marnovandermaas

Thanks for putting this together. Some initial comments from my side.

marnovandermaas · 2026-10-28T13:11:25Z

+  upstream: {
+    url: "https://github.com/openhwgroup/cvfpu.git",
+    // CVFPU submodule revision selected by the pinned CVA6 RVY core.
+    rev: "106251e502747f17d931a20db0bdbab9e1a6c2ff",


Is this revision also a branch name somewhere? The pinning itself can be done using the lock file.

It's awkward because we really want the one in CVA6. However, I believe that is tracking an upstream branch. Is the flow to get the specific commit we need to just manually edit the lock file?

I think this makes sense; the vendoring target by default uses the revision in the lock file, and only pulls in from the head of the branch when run with the --update flag. If I've understood it. I've done this now.

marnovandermaas · 2026-10-28T13:13:12Z

+  always_ff @(posedge __clk) begin \
+    if (__load) __q <= __d; \
+  end


Can we build this using the prim flop asserts?

I've improved this now, and it requires a patch to the veondored lowrisc_ip repo. I guess this should be implemented upstream.

0006_add_resetless_flop_macro.patch

I think you've made this work without the patch now right?

We've made the changes to the vendored-in files, and also committed the patch, so it should be that revendoring will make these changes again when they are pulled in. Maybe it is noteworthy that we needed the additional variant for cva6 + fpu, and the upstream lowrisc_ip repo might want to fold them in at some point.

marnovandermaas

Thanks for the updates, they are looking better now. The Lint is still failing. You will need to update https://github.com/lowRISC/mocha/blob/main/hw/vendor/REUSE.toml to get reuse to pass.

marnovandermaas · 2026-11-05T09:32:06Z


  upstream: {
    url: "https://github.com/lowRISC/cva6-cheri.git",
+    // Mocha integration branch with RVY 0.9.10 support; revision pinned in the lock file.


No need for this comment.

marnovandermaas · 2026-11-05T09:34:15Z

+      # RVY 0.9.10 toolchain, pinned to rvy-0910-wip (2026-10-20).
+      llvm_cheri = lrPkgs.llvm_cheri.overrideAttrs (_: {
+        version = "20.0.0-rvy-0910-457ae0c4c4a9";
+        src = pkgs.fetchFromGitHub {
+          owner = "Capabilities-Limited";
+          repo = "cheri-alliance-llvm-project";
+          rev = "457ae0c4c4a969882b0c26004920d8bfe51cc395";
+          hash = "sha256-+0Ec4rut3F2JvNtq/HGEXefbIvKCDHHSyP1nPo4Z6mY=";
+        };
+      });


This change shouldn't be necessary any more with the LLVM in our Nix cache.

marnovandermaas · 2026-11-05T09:36:26Z

-For maximum tracing performance, omit `--threads 2`.
-For maximum non-tracing performance, or when using Verilator v5.048 onwards, omit `--trace-threads 2`.
+The `-j 4` argument enables parallel C++ compilation, while `--threads 2` enables two simulation threads.
+Verilator 5.048 and later ignore the deprecated `--trace-threads` option.


This last sentence about trace-threads can be removed since we don't use that option anymore after this change.

marnovandermaas · 2026-11-05T09:38:54Z

+      verilator = lrPkgs.verilator_5_048.overrideAttrs (old: {
+        version = "5.054";
+        src = pkgs.fetchFromGitHub {
+          owner = "verilator";
+          repo = "verilator";
+          rev = "v5.054";
+          hash = "sha256-YCCcFA7Mq7SjK6yHldT0rpS1FwXc5C8mgzcJD/imbEw=";
+        };


Are you overriding the v5.048 rules with v5.054? Wouldn't it be better to create a new target instead?

I've updated our reference to your lowrisc-nix, and now point to lrPkgs.verilator_5_054

marnovandermaas · 2026-11-05T09:39:19Z

      verilator:
        mode: lint-only
        verilator_options:
+          # Verilator 5.040 crashes in V3DfgSynthesize on the RVY HPDCache


Is this still true for 5.054?

The fno-dfg-post-inline is no longer necessary; I've removed it now.

marnovandermaas · 2026-11-05T09:42:13Z

-        };
-      });
-
+      llvm_cheri = lrPkgs.llvm_cheri_rvy_0910;


Ah, I see you've change it here. Can you rebase and fold this back into the commit where you introduced this?

I believe this is no longer in the history.

marnovandermaas · 2026-11-05T09:42:46Z

    url: "https://github.com/openhwgroup/cvfpu.git",
-    // CVFPU submodule revision selected by the pinned CVA6 RVY core.
-    rev: "106251e502747f17d931a20db0bdbab9e1a6c2ff",
+    rev: "develop",


Can you fold this into your previous commit?

I believe this is no longer in the history.

marnovandermaas · 2026-11-05T09:43:41Z

-    // Divide/square-root submodule revision selected by the pinned CVFPU.
-    rev: "86e1f558b3c95e91577c41b2fc452c86b04e85ac",
+    // The lock file pins the divide/square-root submodule revision selected by CVFPU.
+    rev: "master",


Can you fold this into the previous commit? And remove the comment about the lock file since this is true for all vendor files.

marnovandermaas · 2026-11-05T09:44:28Z

+// Flip-Flop with no reset
+`define FFNR(__q, __d, __clk = clk_i) \
+  `PRIM_FLOP_NR(__d, __q, __clk)
+


Nice one! Can you fold this into where you introduced FFLNR in the first place?

Ok, this is done now!

Import the mocha integration branch at c1eda9b54e7684c2c39926118405f5b1b93e4f17 using util/vendor.py --update.

…the memory-controller change, but preserves the depth-one buffer pointer fix.

Use lowrisc-nix llvm_cheri_rvy_0910 consistently for the shell, FPGA helpers and CHERI toolchain. Export CHERI_LLVM_BIN for explicit CMake compiler selection.

Set integer mode through hperms, matching the RVY 0.9.9 capability structure.

Add the AES and trigger packages and implementation modules required by the updated CVA6 sources.

Pin Verilator 5.054 and the lowrisc-nix input it builds on. Add scoped provisional waivers for vendor and integration diagnostics and remove deprecated trace-thread options from the documented and CI build commands.

Update capability instructions, register names and address CSRs in startup, trap handling and inline assembly. Use lly/lgy directly for symbol addresses, and account for YPERMC clearing permissions and RVH being disabled. Select rv64ymac_zyhybrid and replace the old ISA feature check with __riscv_zyhybrid; leave the change to ABI-based selection for a separate commit. Audit against RVY 0.9.10: the ported code does not use PACKY, the old YHIR encoding, or the relocated CHERI CSRs. The numeric mtvec, mscratch and mepc indices remain unchanged. Compile the affected purecap and vanilla sources with the pinned RVY 0.9.10 LLVM toolchain.

Use __CHERI_PURE_CAPABILITY__ for startup, trap layouts, MMIO pointers, pointer formatting and capability tests. ISA support alone does not imply that ordinary C pointers or uintptr_t are capabilities. Keep an explicit Zyhybrid requirement for purecap startup because the boot ROM enters in integer mode.

Track CVFPU develop and fpu_div_sqrt_mvp master in vendor descriptions. The separate import locks the revisions selected by CVA6 and CVFPU.

Run the vendor scripts to import the pinned CVFPU and fpu_div_sqrt_mvp revisions and generate their lock files.

Use the F and D settings from the CVA6 configuration and include CVFPU, its divide/square-root dependency, and the CVA6 FPU wrapper in the build. Add the register macro defaults and no-reset variant required by FPnew.

Select the debug-unit revision used by lowRISC/cva6-cheri mocha. Rebase Mocha primitive, wider DMI and reset-pending adaptations; upstream already contains the hart-select and TAP-reset fixes.

Update code from upstream repository https://github.com/Capabilities- Limited/riscv-dbg.git to revision 7fbcff1d606d2193be6517ac1b736c9f85983e5e Signed-off-by: Peter Rugg <peter.rugg@capabilitieslimited.co.uk>

Terminate the debug-module chain explicitly and document how the CVA6 configuration selects the CHERI exception and re-entry vectors. Update the narrow lint waiver for the larger debug ROM and document RVY-aware debugging tools. Validation: Verilator simulator build passed; the existing GDB/OpenOCD regression passed reset/halt, breakpoint, register and memory checks. A locked vendor import reproduces the imported sources. Capability-register inspection using RVY-aware GDB and hardware FPGA testing remain unverified.

marnovandermaas self-requested a review October 28, 2026 12:46

marnovandermaas reviewed Oct 28, 2026

View reviewed changes

jonwoodruff force-pushed the update-RVY branch 2 times, most recently from 9db8a90 to c6f8609 Compare November 4, 2026 17:53

marnovandermaas reviewed Nov 5, 2026

View reviewed changes

jonwoodruff force-pushed the update-RVY branch 5 times, most recently from 314fb40 to b329682 Compare November 5, 2026 14:14

joncapltd changed the title ~~DO NOT MERGE In-progress update to rvy 0.9.10~~ Update to rvy 0.9.10 Nov 5, 2026

jonwoodruff and others added 16 commits November 7, 2026 11:13

Update cva6_cheri to lowRISC/cva6-cheri@c1eda9b5

c78d31c

Import the mocha integration branch at c1eda9b54e7684c2c39926118405f5b1b93e4f17 using util/vendor.py --update.

Update HPDCache patch to apply against upstream HPDCache. This drops …

086d399

…the memory-controller change, but preserves the depth-one buffer pointer fix.

Select the upstream RVY 0.9.10 LLVM package

77c581f

Use lowrisc-nix llvm_cheri_rvy_0910 consistently for the shell, FPGA helpers and CHERI toolchain. Export CHERI_LLVM_BIN for explicit CMake compiler selection.

Update HPDCache from cva6-zcheri-support at 8924e0d7

90e667c

Update reset capability integer-mode field for RVY

5ae4a77

Set integer mode through hperms, matching the RVY 0.9.9 capability structure.

Include RVY AES and trigger sources in CVA6 manifest

e3c7b89

Add the AES and trigger packages and implementation modules required by the updated CVA6 sources.

Use Verilator 5.054 for RVY simulation and lint

8953db7

Pin Verilator 5.054 and the lowrisc-nix input it builds on. Add scoped provisional waivers for vendor and integration diagnostics and remove deprecated trace-thread options from the documented and CI build commands.

[vendor] Configure CVFPU and divide/square-root upstream branches

bee48bc

Track CVFPU develop and fpu_div_sqrt_mvp master in vendor descriptions. The separate import locks the revisions selected by CVA6 and CVFPU.

[vendor] Import CVFPU and divide/square-root sources

865b094

Run the vendor scripts to import the pinned CVFPU and fpu_div_sqrt_mvp revisions and generate their lock files.

[mocha] Enable single- and double-precision floating point

a0a0ffe

Use the F and D settings from the CVA6 configuration and include CVFPU, its divide/square-root dependency, and the CVA6 FPU wrapper in the build. Add the register macro defaults and no-reset variant required by FPnew.

Add license information for the FPU.

9127eb0

[vendor] Configure the CVA6 CHERI debug unit

76662d9

Select the debug-unit revision used by lowRISC/cva6-cheri mocha. Rebase Mocha primitive, wider DMI and reset-pending adaptations; upstream already contains the hart-select and TAP-reset fixes.

Update pulp_riscv_dbg to Capabilities-Limited/riscv-dbg@7fbcff1

57b7f6d

Update code from upstream repository https://github.com/Capabilities- Limited/riscv-dbg.git to revision 7fbcff1d606d2193be6517ac1b736c9f85983e5e Signed-off-by: Peter Rugg <peter.rugg@capabilitieslimited.co.uk>

PRugg-Cap force-pushed the update-RVY branch from fac1114 to 666eb48 Compare November 7, 2026 11:14

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joncapltd commented Oct 22, 2026

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