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[sram,dv] Implement the AXI SRAM vplan tests and DV environment - #764

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tchilikov-semify:sram_verification
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tchilikov-semify:sram_verification

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@tchilikov-semify tchilikov-semify changed the title [sram,dv] Implement the AXI SRAM vplan and DV environment [sram,dv] Implement the AXI SRAM vplan tests and DV environment Oct 22, 2026
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tchilikov-semify force-pushed the sram_verification branch 5 times, most recently from b749636 to 301fab0 Compare November 3, 2026 18:59
- Enables the chip to be driven from the port of the CVA6 with an AXI
driver instead of software.
- Adds a bridge to convert between the geometry of the CVA6 and AXI
driver.
- Adds a knob in the form of a SystemVerilog config to choose whether
the CVA6 or AXI driver bridge is elaborted in.
@tchilikov-semify
tchilikov-semify force-pushed the sram_verification branch 2 times, most recently from 67490bd to 0630ee8 Compare November 5, 2026 14:42
Add a smoke test for the axi_driver_to_cva6_bridge build mode. With
CVA6 replaced by the AXI driver, it writes random words to SRAM through
the CVA6 host port, then reads them back and checks them.

The test is added to the smoke regression.
Add a UVM environment with a scoreboard that checks read data and CHERI
tags against a reference model, functional coverage of tag reads and
writes, and a base vseq of read and write helpers. Add the rst_sanity and
write_read tests and register the sim cfg.
Add directed tests for the verification plan's data path and CHERI tag
items, two randomised tests and a smoke regression, and point the vplan
at them.
Add an SVA module that checks the geometry, tag-write strobes, 4KB burst
boundaries, response latency and read tags, bind it into every axi_sram
instance so the block tb and the top-level build both carry it, and
point the vplan at it.
Add two tests that check from the CVA6 host port that the SRAM's first
and last words round-trip and that addresses outside it return DECERR.
Move the smoke test's helpers into a shared base vseq.

@martin-velay martin-velay left a comment

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Commits 1 and 2 change every top-level build (sim_tops is now tb_cfg), not just the SRAM tests. Could the PR description say so and list what you ran, with the expected failures?

// A capability read is a two-beat burst and its region owns a single tag bit, so both beats
// return the same value. Excluded is a tag write landing inside the burst, which the manager has
// not ordered against the read: the beats are separate memory accesses, so either may see it.
`ASSERT(CapReadRuserBeatsAgree_A,

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af8sx6 lets the SRAM return RUSER (1,0) or (0,1) to invalidate a capability, since the core ANDs the two beats. CapReadRuserBeatsAgree_A and the per-beat tag compare in the scoreboard both reject that, and the assertion is now in every top build too. Could the #780 decision cover it, with both checks comparing the AND of the two beats if af8sx6 stays?

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Good point. I've captured this unknown in issue #783, since its different from #780. I'm currently not sure what could trigger the SRAM to return a (1,0) or a (0,1) capability, so we need some clarification.

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@martin-velay this PR is dependent on #761, so the first two commits are actually just a clone/copy of #761. They will eventually be replaced by the final contents of #761 once its merged.

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2 participants