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[mailbox,dv] Add the block-level UVM environment and V1 tests - #767
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Keep the register description, testplan and vPlan in the IP's data directory, as OpenTitan does. The RTL stays vendored in hw/vendor/pulp_axi. Use the current copyright header. Signed-off-by: Martin Velay <mvelay@lowrisc.org>
Start block verification of the PULP mailbox in Mocha's two-port, 64-bit, depth-3 configuration (lowRISC#173). Connect each AXI manager's monitor to a register predictor that filters errors and applies the whole-word WIRQT/RIRQT clamp. Check FIFO data, order, responses and STATUS against the specification. Keep states consistent with the full observed history while allowing overlapping accesses to take effect in either order, since cross-port latency is unspecified. Exercise serial and concurrent transfers in mailbox_smoke. Use a separate register parent per access to avoid swapping UVM 1.2 responses between ports. Signed-off-by: Martin Velay <mvelay@lowrisc.org>
Exercise reset values, readback, individual bits and address aliasing on both ports. Run UVM's single-register bit-bash sequence and local reset, read/write and aliasing sequences. Directed values cross the threshold clamp boundary on every seed. Exclude MBOXR, MBOXW and CTRL with tags in the register description, as OpenTitan does, because of FIFO side effects and open access semantics in lowRISC#755. Leave writes to read-only registers and IRQS W1C field checks to V2. Compare volatile fields immediately after reset. This reproduces lowRISC#754: IRQS reads 0x3 rather than 0x0 on both ports. Keep the check enabled until the RTL is fixed. Signed-off-by: Martin Velay <mvelay@lowrisc.org>
Include the mailbox configuration in mocha_sim_cfgs.hjson so batch runs can select the new block tests. Signed-off-by: Martin Velay <mvelay@lowrisc.org>
dvsim builds a regression for each testplan stage and logs an error for every listed test that the sim cfg does not define. List a testpoint's tests once they exist, as OpenTitan does; until then dvsim reports the testpoint as not run. Signed-off-by: Martin Velay <mvelay@lowrisc.org>
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Second part of the mailbox block-level DV (#173), on top of the testplan and register description from #756.
axi_mgr_agentper port, a register model per port with a predictor that models the WIRQT/RIRQT clamp, and a scoreboard that models both FIFOs from the documentation.mailbox_smoke,mailbox_csr_hw_reset,mailbox_csr_rw,mailbox_csr_bit_bashandmailbox_csr_aliasing.mailbox_csr_hw_resetfails until #754 is fixed: IRQS reads 0x3 on both ports.Where the documentation leaves things open (#755), the tests clamp WIRQT/RIRQT on the whole written word, expect ERROR to reset to 0 and reserved bits to read 0, and leave MBOXW and CTRL out of the CSR tests.
Tested on Xcelium only: smoke, rw, bit_bash and aliasing pass on 5 seeds each.