[tchilikov-semify]

In the mailbox we use fifo_v3s, where the fifo_v3 is a wrapper of the prim_fifo_sync. prim_fifo_sync contains a wready_o and a full_o signal to communicate its conditions, but the fifo_v3 wrapper flattens these into one single full_o signal, as follows:

assign full_o  = full | err | ~wready; 

The issue is that the nested prim_fifo_sync keeps its wready_o signal as unready for an extra cycle after reset, which is reported as full by the fifo_v3. The mailbox after reset reads this full value of the fifo_v3, and latches the value into the IRQ status register, which triggers an interrupt as soon as interrupts are enabled if it is not cleared. We shouldn't have to do this clear before enabling interrupts.

If we alter the wrapper to not report full after a reset, even though the nested prim_fifo_sync is not ready, we risk the issue of silently losing data on a write in the case that a write happens at the same time.

Therefore, the better approach is that we instead alter the mailbox so that interrupts for the full condition are not allowed to be set on the cycle directly after a reset, which is anyways not possible, since the fifo cannot be full directly after reset.

This PR closes issue #754

[raylau1]

Thanks, LGTM.