🧩 Starter template for ASIC hardware IP blocks with Vyges metadata, OpenLane integration, and comprehensive documentation
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Apr 30, 2026 - Python
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vyges
Here are 40 public repositories matching this topic...
Configurable, high-performance FFT hardware IP core for ASIC/FPGA. Pipelined radix-2 DIF, 256–4096-point support, 16-bit fixed-point, double-buffered memory, APB/AXI interfaces. Optimized for throughput and low latency.
asic fpga pipeline signal-processing rad verilog digital-signal-processing apb ip-core hardware-ip vyges vyges-ip ix-2
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Nov 15, 2026 - SystemVerilog
Clean-room container for building RTL → GDSII: a slim, pinned open-source EDA toolchain (Yosys · Verilator · OpenROAD · Magic · KLayout · Netgen · ngspice + sky130/gf180 PDKs), built from scratch on GitHub Actions and published to GHCR.
docker magic asic container eda vlsi yosys semiconductor klayout netgen ngspice gdsii physical-design openroad sky130 chip-design gf180mcu open-source-silicon rtl-to-gdsii vyges
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Oct 29, 2026 - Dockerfile
A fully pipelined digital Hilbert transformer IP block for DSP applications including single sideband modulation, amplitude/phase detection, and quadrature signal processing. Optimized for FPGA and ASIC implementations with configurable precision and maximum throughput.
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Oct 8, 2025 - SystemVerilog
Static timing analysis with signal integrity — WNS/TNS sign-off gate, SI/crosstalk + statistical OCV. · Download Loom: https://vyges.com/products/vyges-cli/#install
rust asic digital eda semiconductor silicon opendb signoff static-timing-analysis physical-design signal-integrity open-source-silicon eda-tools vyges sign-off open-silicon vyges-loom
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Nov 15, 2026 - Rust
Design-rule check: a GDS layout + a rule deck in, geometry violations out. · Download Loom: https://vyges.com/products/vyges-cli/#install
rust asic digital analog eda semiconductor mixed-signal opendb signoff gdsii physical-design physical-verification open-source-silicon design-rule-check eda-tools vyges open-silicon vyges-loom
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Nov 15, 2026 - Rust
A configurable UART controller IP with APB interface, FIFO support, and interrupt capabilities. Designed for SkyWater 130nm Open Source PDK with comprehensive verification and OpenLane integration.
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Oct 8, 2025 - SystemVerilog
VyBox Lite: One-click Codespaces environment for trying Vyges chip/IP development in your browser.
eda verilog systemverilog semiconductor cocotb browser-ide github-codespaces chip-design open-source-silicon vyges vyges-ip vybox vybox-lite
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Feb 20, 2026 - JavaScript
Layout-vs-schematic: SPICE netlist comparison with clear divergence diagnostics. · Download Loom: https://vyges.com/products/vyges-cli/#install
rust asic digital analog eda semiconductor mixed-signal silicon lvs opendb signoff physical-design open-source-silicon eda-tools vyges open-silicon vyges-loom layout-vs-schematic
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Nov 15, 2026 - Rust
The part of a design a re-synthesis works on: extracted from the timing graph, written out to ABC as BLIF or a mapped network, and the result put back. · Download Loom: https://vyges.com/products/vyges-cli/#install
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Nov 12, 2026 - Rust
A configurable full adder IP with three implementation approaches (simple XOR/AND, modular half adder, carry lookahead) following Vyges conventions. Includes comprehensive verification with SystemVerilog, UVM, and Cocotb testbenches supporting multiple simulators (Icarus, Verilator, Questa, VCS, Xcelium). Production-ready for ASIC/FPGA w/ 500MHz
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Nov 15, 2026 - Python
📋 Vyges Metadata Specification - Standardized format for hardware IP discovery and integration
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Oct 29, 2026 - HTML
Loom engine: SDC constraint checking and writing
rust asic digital linter eda sdc semiconductor silicon signoff static-timing-analysis timing-constraints open-source-silicon eda-tools vyges open-silicon vyges-loom
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Nov 15, 2026 - Rust
Vyges open-PDK catalog: index.json + full PDK descriptors
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Oct 30, 2026 - Python
Deterministic hypergraph partitioning: multilevel coarsening, initial partitioning and refinement, with small exact ILP solves. · Download Loom: https://vyges.com/products/vyges-cli/#install
rust eda partitioning hypergraph-partitioning placement open-source-silicon eda-tools vyges vyges-loom
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Nov 15, 2026 - Rust
Liberty characterization — SPICE + PDK models to .lib (NLDM + CCS), parallel-SPICE orchestration. · Download Loom: https://vyges.com/products/vyges-cli/#install
rust asic digital eda spice characterization liberty semiconductor silicon opendb physical-design open-source-silicon eda-tools vyges open-silicon vyges-loom
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Nov 15, 2026 - Rust
Public release home for the Vyges CLI — prebuilt binaries + curl/PowerShell installers (catalog, PDK, and Loom-engine installs). Homebrew tap: vyges/homebrew-tap.
rust cli installer eda semiconductor silicon ic-design hardware-design open-source-silicon vyges open-silicon vyges-cli
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Nov 11, 2026
Pinned OR-Tools linear solver (SCIP backend) built with Bazel into one static archive, behind a small C shim and a safe Rust API. · Download Loom: https://vyges.com/products/vyges-cli/#install
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Nov 12, 2026 - Shell
Power-grid analysis on the design database: connectivity check, static IR drop, SPICE export. · Download Loom: https://vyges.com/products/vyges-cli/#install
rust asic eda physical-design power-integrity power-grid electromigration ir-drop open-source-silicon vyges vyges-loom
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Nov 15, 2026 - Rust
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