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Additional tests - #185
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ElioPalleschi wants to merge 35 commits into
Closed
Additional tests#185ElioPalleschi wants to merge 35 commits into
ElioPalleschi wants to merge 35 commits into
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Co-authored by: rgiunti <rg98.lavoro@gmail.com>
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rgiunti
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LGTM. @Navaneeth-KunhiPurayil could you start the CI for this PR? Thanks
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Hi @DiyouS, could you trigger the CI for this PR? Thanks |
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Hi @DiyouS, can you start the CI please? |
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Done |
Co-authored by: rgiunti <rg98.lavoro@gmail.com>
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This pull request introduces support for register load/store instructions with the related tests, and additional tests for other instructions.
This PR is related to this vpu.
Hardware support for new vector instructions
Added support for whole register group load instructions (
VL1RE8/16/32/64,VL2RE8/16/32/64,VL4RE8/16/32/64,VL8RE8/16/32/64) and corresponding store instructions (VS1R,VS2R,VS4R,VS8R) in the main Snitch core module (snitch.sv).Added tests
Added tests for
vfredosum,vmv,vadc,vmadc,vsbc,vmsbc,vlreandvsr.