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Support for register load/store instructions and bug fixes - #32
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ElioPalleschi wants to merge 21 commits into
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* [DOC] adding spatz standalone documentation * [DOC] updated doc reference in readme
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vl<nf>re<eew>.v and vs<nf>r.v and bug fixes
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vl<nf>re<eew>.v and vs<nf>r.v and bug fixes
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October 29, 2026 09:51
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Thanks @ElioPalleschi, it looks good to me.
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* hw: implement FPalt widening * hw: add fp8 -> fp16alt widening * fix typo
* Fix VLSU * VLSU Fix #2 * Fixed vluxei tests, fixed D22 * D27 Fix + updated tests * cleaner code * Fixed D29, Reverted D27 * D25 fix * D26 fix * D29 Fix #2 * D28 Fix * D23 Fix * D27 fix * D26 fix n.2 * VLSU fixes carried over to DoubleBW * Scoreboard and chaining fixes * verilog fixes * spatz_pkg tpl change * Synthesis fix * Synthesis fix n.2 * Synthesis fix n.3 * fix divsqrt_is_shared configuration * Synthesis fix n.4 * Synthesis fix n.5 --------- Co-authored-by: rgiunti <riccardo.giunti@chips.it>
…es' into epalleschi/vfu_and_vlsu_additions
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This pull request introduces support for the
vl<nf>re<eew>.vandvs<nf>r.vinstructions and fixes tovfredosum.v,vmv.x.s,vadc.v,vmadc.v,vsbc.vandvmsbc.v. After the synthesis, the new vpu module's area has increased by 0.5%.These changes are verified by the tests introduced by this PR.
Support for
vl<nf>re<eew>.vandvs<nf>r.vAdded decoding, control, and execution support for the
VLRE(VL1RE8_V,VL2RE8_V, etc.) andVSR(VS1R_V,VS2R_V, etc.) instructions. They are handled by converting them into equivalent flat, unmasked, unit-stride byte transfers.vfredosum.vfixBefore this change, vfredosum was executed as a parallel tree, like vfredusum.
vmv.x.sfixOriginally, the VFU simply copied the entire lower word of a vector register into the scalar register without extracting element 0 or sign-extending it to XLEN according to the active element width.
is_int_scalar_moveto theop_arithstruct to differentiate it from other scalar-producing operations, and set it to 1 forvmv.x.s.scalar_resultassignment to adapt it forvmv.x.s.vadc.v,vmadc.v,vsbc.v,vmsbc.vfixThese instructions didn't use the carry-in, and instead treated v0 as a write mask.